Low-Power Multi-algorithm Programmable Seizure Detection Sub-processor in 65nm bulk-Si CMOS Integrated Circuit
Abstract number :
3.077
Submission category :
1. Translational Research
Year :
2011
Submission ID :
15143
Source :
www.aesnet.org
Presentation date :
12/2/2011 12:00:00 AM
Published date :
Oct 4, 2011, 07:57 AM
Authors :
H. S. Markandeya, S. Raghunathan, K. Roy, P. P. Irazoqui
Rationale: Neuromodulation by means of electrical, chemical or even optical stimulation is rapidly emerging as a promising alternative therapy for patients that do not respond to AEDs or are not candidates for surgical treatments. Responsive intervention is believed to impact the efficacy of this therapy by critically increasing its temporal and spatial specificity. Efficient and low-power seizure detection algorithms present the key to realizing a fully integrated implantable prosthesis capable of responsively delivering therapy to the epileptogenic focus. Seizure detection will also allow clinicians and researchers to track the dynamics of epileptic seizures over time to better understand the disease. We present a low-power seizure detection sub-processor which utilizes multiple hardware-optimized detection features , allowing for programmable logical combinations to realize high efficacy patient-specific seizure detection algorithms. The integrated circuit size allows for easy integration into closed-loop neuromodulation systems.Methods: The primary module consists of four feature extraction blocks: energy, coastline, non-linear energy and Hjorth parameter. Each of these features evaluates independently on a digitized input data stream. The intermediate computed values are compared against programmable thresholds generating 4 streams of signals indicating independent seizure detections, based on the feature. A Logic Selector block is provided which can be programmed to select a combination from a finite number of logical permutations of the 4 feature outputs in order to determine the final system output. The features used are optimized for low-power hardware implementation, making appropriate algorithmic trade-offs to facilitate computational ease and therefore simple digital implementations. A secondary built-in-self-test module verifies the functioning of each algorithm independently as well as the logic selector in an automated manner, thereby reducing the need for extensive testing of the hardware, benefiting mass production. Results: The system was implemented using TSMC 65nm bulk-Si technology within an area of 0.068mm2. With an average power consumption of 95- W (5 W dynamic, 90 W leakage at 1-MHz) from a supply of 1- V. 10-bit threshold programmability allows for highly accurate control over algorithm sensitivity and specificity on an individual patient basis. We report the efficacy of optimized combinations of these features from data obtained using 5 epileptic rats (Kainic acid model).Conclusions: Optimized and programmable seizure detection processors such as mentioned in this abstract allow for direct integration into battery-powered neuromodulation implants. These eliminate the need to wirelessly transmit data to an external processor for computation and thereby significantly impact the longevity of the implant.
Translational Research